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Impact of CMOS Scaling and Technology Options on ESD Reliability

dc.contributor.authorMahadeva Iyer, Natarajan
dc.contributor.authorThijs, Steven
dc.contributor.authorVassilev, Vesselin
dc.contributor.authorTremouilles, David
dc.contributor.authorLinten, Dimitri
dc.contributor.authorGroeseneken, Guido
dc.date.accessioned2021-10-16T03:11:47Z
dc.date.available2021-10-16T03:11:47Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10834
dc.sourceIIOimport
dc.titleImpact of CMOS Scaling and Technology Options on ESD Reliability
dc.typeOral presentation
dc.contributor.imecauthorThijs, Steven
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecThijs, Steven::0000-0003-2889-8345
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.source.peerreviewno
dc.source.conferenceMRS International Conference on Advanced Materials (IUMRS-ICAM)
dc.source.conferencedate4/07/2005
dc.source.conferencelocationSingapore Singapore
imec.availabilityPublished - imec
imec.internalnotesOnly abstract published in MRS


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