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Potential and technological challenges for silicon and hetero-structure tunnelFETs for low-power applications

dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-19T12:52:30Z
dc.date.available2021-10-19T12:52:30Z
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18711
dc.sourceIIOimport
dc.titlePotential and technological challenges for silicon and hetero-structure tunnelFETs for low-power applications
dc.typeOral presentation
dc.source.peerreviewno
dc.source.conferenceBITS 1st World Congress on Nano S&T
dc.source.conferencedate23/10/2011
dc.source.conferencelocationDalian China
imec.availabilityPublished - imec


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