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Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

dc.contributor.authorGupta, A.
dc.contributor.authorMertens, H.
dc.contributor.authorTao, Z.
dc.contributor.authorDemuynck, S.
dc.contributor.authorBommels, J.
dc.contributor.authorArutchelvan, G.
dc.contributor.authorDevriendt, K.
dc.contributor.authorPedreira, O. Varela
dc.contributor.authorRitzenthaler, R.
dc.contributor.authorWang, S.
dc.contributor.authorRadisic, D.
dc.contributor.authorKenis, K.
dc.contributor.authorTeugels, L.
dc.contributor.authorSebaai, F.
dc.contributor.authorLorant, C.
dc.contributor.authorJourdan, N.
dc.contributor.authorChan, B. T.
dc.contributor.authorZahedmanesh, H.
dc.contributor.authorSubramanian, S.
dc.contributor.authorSchleicher, F.
dc.contributor.authorHopf, T.
dc.contributor.authorPeter, A.
dc.contributor.authorRassoul, N.
dc.contributor.authorDebruyn, H.
dc.contributor.authorDemonie, I
dc.contributor.authorSiew, Y.
dc.contributor.authorChiarella, T.
dc.contributor.authorBriggs, B.
dc.contributor.authorZhou, D.
dc.contributor.authorRosseel, E.
dc.contributor.authorDe Keersgieter, A.
dc.contributor.authorCapogreco, E.
dc.contributor.authorLitta, E. Dentoni
dc.contributor.authorBoccardi, G.
dc.contributor.authorBaudot, S.
dc.contributor.authorMannaert, G.
dc.contributor.authorBontemps, N.
dc.contributor.authorSepulveda, A.
dc.contributor.authorMertens, S.
dc.contributor.authorKim, M. S.
dc.contributor.authorDupuy, E.
dc.contributor.authorVandersmissen, K.
dc.contributor.authorPaolillo, S.
dc.contributor.authorYakimets, D.
dc.contributor.authorChehab, B.
dc.contributor.authorFavia, P.
dc.contributor.authorDrijbooms, C.
dc.contributor.authorCousserier, J.
dc.contributor.authorJaysankar, M.
dc.contributor.authorLazzarino, F.
dc.contributor.authorMorin, P.
dc.contributor.authorSanchez, E.
dc.contributor.authorMitard, J.
dc.contributor.authorWilson, C.
dc.contributor.authorHolsteyns, F.
dc.contributor.authorTokei, Z.
dc.contributor.authorHoriguchi, N.
dc.date.accessioned2021-11-02T15:59:09Z
dc.date.available2021-11-02T15:59:09Z
dc.date.issued2020
dc.identifier.issn0743-1562
dc.identifier.otherWOS:000668063000097
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/37742
dc.sourceWOS
dc.titleBuried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
dc.typeProceedings paper
dc.contributor.imecauthorGupta, A.
dc.contributor.imecauthorMertens, H.
dc.contributor.imecauthorTao, Z.
dc.contributor.imecauthorDemuynck, S.
dc.contributor.imecauthorBommels, J.
dc.contributor.imecauthorArutchelvan, G.
dc.contributor.imecauthorDevriendt, K.
dc.contributor.imecauthorPedreira, O. Varela
dc.contributor.imecauthorRitzenthaler, R.
dc.contributor.imecauthorWang, S.
dc.contributor.imecauthorRadisic, D.
dc.contributor.imecauthorKenis, K.
dc.contributor.imecauthorTeugels, L.
dc.contributor.imecauthorSebaai, F.
dc.contributor.imecauthorLorant, C.
dc.contributor.imecauthorJourdan, N.
dc.contributor.imecauthorChan, B. T.
dc.contributor.imecauthorZahedmanesh, H.
dc.contributor.imecauthorSubramanian, S.
dc.contributor.imecauthorSchleicher, F.
dc.contributor.imecauthorHopf, T.
dc.contributor.imecauthorPeter, A.
dc.contributor.imecauthorRassoul, N.
dc.contributor.imecauthorDebruyn, H.
dc.contributor.imecauthorDemonie, I
dc.contributor.imecauthorSiew, Y.
dc.contributor.imecauthorChiarella, T.
dc.contributor.imecauthorBriggs, B.
dc.contributor.imecauthorZhou, D.
dc.contributor.imecauthorRosseel, E.
dc.contributor.imecauthorDe Keersgieter, A.
dc.contributor.imecauthorCapogreco, E.
dc.contributor.imecauthorLitta, E. Dentoni
dc.contributor.imecauthorBoccardi, G.
dc.contributor.imecauthorBaudot, S.
dc.contributor.imecauthorMannaert, G.
dc.contributor.imecauthorBontemps, N.
dc.contributor.imecauthorSepulveda, A.
dc.contributor.imecauthorMertens, S.
dc.contributor.imecauthorKim, M. S.
dc.contributor.imecauthorDupuy, E.
dc.contributor.imecauthorVandersmissen, K.
dc.contributor.imecauthorPaolillo, S.
dc.contributor.imecauthorYakimets, D.
dc.contributor.imecauthorChehab, B.
dc.contributor.imecauthorFavia, P.
dc.contributor.imecauthorDrijbooms, C.
dc.contributor.imecauthorCousserier, J.
dc.contributor.imecauthorJaysankar, M.
dc.contributor.imecauthorLazzarino, F.
dc.contributor.imecauthorMorin, P.
dc.contributor.imecauthorSanchez, E.
dc.contributor.imecauthorMitard, J.
dc.contributor.imecauthorWilson, C.
dc.contributor.imecauthorHolsteyns, F.
dc.contributor.imecauthorTokei, Z.
dc.contributor.imecauthorHoriguchi, N.
dc.identifier.eisbn978-1-7281-6460-1
dc.source.numberofpages2
dc.source.peerreviewyes
dc.source.conferenceIEEE Symposium on VLSI Technology and Circuits
dc.source.conferencedateJUN 15-19, 2020
imec.availabilityUnder review


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220.500.12860/37742.22021-12-15T09:26:55Zvalidation by library/open access desk
120.500.12860/37742*2021-11-02T15:59:09Z

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