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Optimized Threshold Implementations: Minimizing the Latency of Secure Cryptographic Accelerators

dc.contributor.authorBozilov, Dusan
dc.contributor.authorKnezevic, Miroslav
dc.contributor.authorNikov, Ventzislav
dc.date.accessioned2021-11-02T16:01:14Z
dc.date.available2021-11-02T16:01:14Z
dc.date.issued2020
dc.identifier.isbn978-3-030-42067-3
dc.identifier.issn0302-9743
dc.identifier.otherWOS:000659649800002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/37885
dc.sourceWOS
dc.titleOptimized Threshold Implementations: Minimizing the Latency of Secure Cryptographic Accelerators
dc.typeProceedings paper
dc.contributor.imecauthorBozilov, Dusan
dc.identifier.doi10.1007/978-3-030-42068-0_2
dc.identifier.eisbn978-3-030-42068-0
dc.source.numberofpages20
dc.source.peerreviewyes
dc.source.beginpage20
dc.source.endpage39
dc.source.conference18th International Conference on Smart Card Research and Advanced Applications (CARDIS)
dc.source.conferencedateNOV 11-13, 2019
dc.source.conferencelocationPrague
dc.source.volume11833
imec.availabilityUnder review


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220.500.12860/37885.22021-11-18T16:38:52Zvalidation by library/open access desk
120.500.12860/37885*2021-11-02T16:01:14Z

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