Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow

Abstract

In the past few years, the demand for computationally intensive applications, such as digital signal processing or convolutional neural networks, has grown exponentially. As they often rely on a significant number of multiply-and-accumulate cells, it is crucial to optimize their area and cost. Recently, a 3D Nanofabric flow has been proposed, where logic circuits are designed by stacking N identical vertical tiers on top of each other. Exploiting identical layers allows a fabrication process similar to the Vertical-NAND flash, where all the layers can be patterned at once. While the 3D Nanofabric flow presents several layout constraints (single metal routing and identical vertical layers), it can decrease the area by around one order of magnitude, leading to area-efficient and cost-effective circuits. In this paper, we propose to use the 3D Nanofabric process flow to design low-area multipliers. As multipliers can be designed using a regular array organization, we show how they can be spread across multiple vertical layers using the 3D Nanofabric flow, while respecting the different layout constraints. We then provide thorough circuit-level evaluations, including parasitics, to showcase the benefits of our proposed 3D multipliers at the circuit-level. We show that by stacking up to 64 layers to build a 64-input bit multiplier, the area and area-delay-product can be decreased by 28.6x and 25.5x, respectively, compared to a traditional 2D implementation using a 28nm FDSOI technology, with only a 10% and 35% delay and power consumption overheads, respectively.