Dual-Input Pseudo-CMOS Logic for Digital Applications on Flexible Substrates

Abstract

A new standard cell topology, Dual-Input Pseudo-CMOS (DIPC), for dual-gate Indium-Gallium-Zinc-Oxide (IGZO) thin-film transistor (TFT) technology on flexible substrates is presented. The proposed logic topology is compared with the conventional Pseudo-CMOS in terms of robustness (noise margin), speed performance, power consumption and area usage. This work shows that the back-gate of a TFT can be used as a separate parallel transistor reducing the number of devices in logic gates without compromising the speed and the power. Two 32-bit code generators for RFID transponders with both libraries have been designed and fabricated using n-type only TFTs with a channel length of 5 mu m. The proposed topology allowed to reduce the number of TFTs by 24% and the chip consumes only 2.2 mu W of power at 4 kHz clock frequency and 1 V of supply voltage. This work also forecasts that the number of TFTs can be reduced strongly by using the proposed DIPC topology for complex designs such as arithmetic logic units and microprocessors.