Recently added

Channel gain for a wrist-to-arm scenario in the 55-65 GHz frequency band

Thielens, Arno; Aminzadeh, Reza; Martens, Luc; Joseph, Wout; Rabaey, Jan (2019-10)

Patterning challenges for beyond 3nm logic devices: Example of an interconnected magnetic tunnel junction

Thiam, Arame; Wan, Danny; Souriau, Laurent; Babaei Gavan, Khashayar; Rassoul, Nouredine; Swerts, Johan; Couet, Sebastien; Raymenants, Eline; Jussot, Julien; Trivkovic, Darko; Ercken, Monique; Wilson, Chris; Radu, Iuliana (2019)

Exploring resist options for EUV layers of IMEC N5 CMOS vehicle

Thiam, Arame; Paolillo, Sara; Lazzarino, Frederic; Ercken, Monique; Wong, Patrick; Charley, Anne-Laure (2019)

A new weighted NMF algorithm for missing data interpolation and its application to speech enhancement

Thakallapalli, S.; Gangashetty, S.; Madhu, Nilesh (2019)

Ru CMP for advanced metallization

Teugels, Lieve; Heylen, Nancy; Ridremont, Romain; van der Veen, Marleen; Yamanaka, Tatsuya; Yamada, Yuuya; Nishimura, Kouhei; Buch, Xavier; Hiro, Akito; Vega Gonzalez, Victor; Struyf, Herbert (2019-09)

2D-3D integration of high- $j dielectric with 2D heterostructures for opto-electronic applications

Terres, B.; Agarwal, H.; Orsini, L.; Montanaro, A.; Sorianello, V.; Van Thourhout, Dries; Watanabe, K.; Taniguchi, T.; Romagnoli, M.; Koppens, F. (2019)

FEOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT)

Tao, Zheng; Li, Waikin; Kim, Min-Soo; Devriendt, Katia; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Sepulveda Marquez, Alfonso; Jourdan, Nicolas; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Matagne, Philippe; Ragnarsson, Lars-Ake; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Altamirano Sanchez, Efrain; Lee, James; Li, YiSuo; Kanazawa, Kenichi; Harada, Nozomu; Masuoka, Fujio (2019)

Full-duplex analog radio-over-fiber system based on an integrated transceiver with a silicon microring modulator and a transfer-printed III-V photodetector

Tang, Zhenzhou; Zhang, Jing; Pan, Shilong; Roelkens, Gunther; Van Thourhout, Dries (2019)

Design of A D-band transformer-based neutralized class-AB power amplifier in silicon technologies

Tang, Xinyan; Medra, Alaaeldien; Nguyen, Johan; Khalaf, Khaled; Debaillie, Bjorn; Wambacq, Piet (2019)

Scaled spin-wave majority gate

Talmelli, Giacomo; Devolder, Thibaut; Radu, Iuliana; Adelmann, Christoph; Ciubotaru, Florin (2019)

In-line spin wave majority gate

Talmelli, Giacomo; Devolder, Thibaut; Heyns, Marc; Radu, Iuliana; Adelmann, Christoph; Ciubotaru, Florin (2019)

Spin-wave majority gates

Talmelli, Giacomo; Adelmann, Christoph; Devolder, Thibaut; Träger, Nick; Gräfe, Joachim; Heyns, Marc; Radu, Iuliana; Ciubotaru, Florin (2019)

Linewidth and roughness measurement of SAOP by using FIB and planer-TEM as reference metrology

Takamasu, Kiyoshi; Takahashi, Satoru; Kawada, Hiroki; Ikota, Masami; Decoster, Stefan; Lazzarino, Frederic; Lorusso, Gian (2019)

Impact of sidewall etching on the dynamic performance of GaN-on-Si E-mode transistors

Tajalli, A.; Canato, E.; Nardo, A.; Meneghini, M.; Stockman, Arno; Moens, P.; Zanoni, E.; Meneghesso, G. (2019)

Reflections on: Triple storage for random-access versioned querying of RDF archives

Taelman, Ruben; Vander Sande, Miel; Van Herwegen, Joachim; Mannens, Erik; Verborgh, Ruben (2019)

Block-anti-circulant unbalanced oil and vinegar

Szepienic, A.; Preneel, Bart (2019)

Towards systematic specification of non-functional requirements for sharing economy services

Symeonidis, I.; Schroers, J.; Mustafa, M.A.; Biczok, G. (2019)

Material and integration challenges of magnetic tunnel junctions in advanced spintronic applications

Swerts, Johan; Couet, Sebastien; Carpenter, Robert; Liu, Enlong; Hon, Kwan; Mertens, Sofie; Sankaran, Kiroubanand; Rao, Siddharth; Kim, Woojin; Garello, Kevin; Kundu, Shreya; Souriau, Laurent; Yasin, Farrukh; Sharif Md. Sadaf, Sharif; Van Elshocht, Sven; Crotti, Davide; Kar, Gouri Sankar (2019)

WS2 MOSFETs: significant performance improvement with Mg contacts

Sutar, Surajit; Mongillo, Massimo; El Kazzi, Salim; Asselberghs, Inge; Huyghebaert, Cedric; Caymax, Matty; Lin, Dennis; Radu, Iuliana (2019)

RF characterization of mold compound materials and high-Q passives integrated using fan-out wafer-level packaging technology

Sun, Xiao; Slabbekoorn, John; Velenis, Dimitrios; Miller, Andy; Van der Plas, Geert; Beyne, Eric (2019)

Conference contributions: Recent submissions

Channel gain for a wrist-to-arm scenario in the 55-65 GHz frequency band ﻿

Patterning challenges for beyond 3nm logic devices: Example of an interconnected magnetic tunnel junction ﻿

Exploring resist options for EUV layers of IMEC N5 CMOS vehicle ﻿

A new weighted NMF algorithm for missing data interpolation and its application to speech enhancement ﻿

Ru CMP for advanced metallization ﻿

2D-3D integration of high- $j dielectric with 2D heterostructures for opto-electronic applications ﻿

FEOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT) ﻿

Full-duplex analog radio-over-fiber system based on an integrated transceiver with a silicon microring modulator and a transfer-printed III-V photodetector ﻿

Design of A D-band transformer-based neutralized class-AB power amplifier in silicon technologies ﻿

Scaled spin-wave majority gate ﻿

In-line spin wave majority gate ﻿

Spin-wave majority gates ﻿

Linewidth and roughness measurement of SAOP by using FIB and planer-TEM as reference metrology ﻿

Impact of sidewall etching on the dynamic performance of GaN-on-Si E-mode transistors ﻿

Reflections on: Triple storage for random-access versioned querying of RDF archives ﻿

Block-anti-circulant unbalanced oil and vinegar ﻿

Towards systematic specification of non-functional requirements for sharing economy services ﻿

Material and integration challenges of magnetic tunnel junctions in advanced spintronic applications ﻿

WS2 MOSFETs: significant performance improvement with Mg contacts ﻿

RF characterization of mold compound materials and high-Q passives integrated using fan-out wafer-level packaging technology ﻿