3D SoC integration, beyond 2.5D chiplets

Abstract

2.5D "Chiplet" approaches allow for a dense integration of independently designed & fabricated ICs. However, this inherently adds a significant interconnect latency, therefore limiting the application to latency-tolerant applications. This added latency can be eliminated by introducing a "3D-SoC" design approach This is an extension of the highly successful 2D System-on-Chip (SoC) design methodology, where the system is automatically partitioned into separate chips that are concurrently designed & interconnected in the 3rd dimension. To realize such 3D-SoC circuits, the 3D interconnect pitch needs to be scaled further beyond the current state-of-the-art. Our current research has demonstrated the feasibility of realizing such interconnections at 7 mu m pitch for die-to-die stacking and 700nm pitch for wafer-to-wafer (W2W).