Tailoring IGZO-TFT architecture for capacitorless DRAM, demonstrating > 10(3)s retention, > 10(11) cycles endurance and L-g scalability down to 14nm

Abstract

We demonstrate a fully 300-mm BEOL-compatible IGZO-based capacitorless DRAM cell with >10(3)s retention and >10(11) endurance lifetime. We reveal the impact of the IGZO-TFT architecture on the memory performance of 2T0C structures, and we select a gate-last integration scheme with buried oxygen tunnel and self-aligned contacts. With this architecture, we demonstrate >100s retention time down to scaled L-g approximate to 14 nm. We prove that by decreasing the gate dielectric thickness the retention time can be significantly improved, while the IGZO thickness scaling enables to skip the defect passivation anneal. We also demonstrate the functionality of 2T0C cells with conformal IGZO deposition, paving the way for full BEOL 3D DRAM integration.