Design, patterning, and process integration overview for 2nm node

Abstract

According to the Power-Performance-Area requirements in advanced technology node, we already scaled down poly pitch (CPP) and metal pitch (MP) which considered as main factors to form standard cell (SDC) area. However, in recent technology nodes, the scaling of CPP and MP started to slow down, due to the physical limitation. To continue to meet the requirements, combined with Design-Technology co-optimization (DTCO), the height of standard cell would become the main factor here, which we could reduce it by reducing the number of tracks. In this paper, we would introduce 3D-IC as one of the design options for 2nm node to keep scaling by reducing the cell height with its specific 3D structure and inserted booster. Also, we would introduce the coming challenges as importing 3D-IC to 2nm technology node.