Refined DC and Low-Frequency Noise Characterization at Room and Cryogenic Temperatures of Vertically Stacked Silicon Nanosheet FETs

Abstract

this work, two types of gate-all-around (GAA) vertically stacked silicon nanosheet (NS) FETs are investigated, the main difference being the vertical distance between the stacked NSs. Principal electrical parameters are estimated at room and liquid nitrogen temperatures using a refined Y-function methodology, the main advantage being that no extra iterative steps are necessary. The results are confirmed using other derivative dc parameter estimation methodologies. Low-frequency noise measurements evidence variability of the flat-band voltage noise and correlation between the noise level and the low field mobility. The dominant flicker noise mechanism is related to the correlated mobility and carrier number fluctuation mechanism with access resistance noise contribution in very strong inversion. The impact of the access resistance on the estimation of the Coulomb scattering coefficient is evidenced.