Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets

Abstract

A novel forksheet (FSH) FET architecture has been proposed earlier, consisting of vertically stacked n- and p-type sheets at opposing sides of a dielectric wall, particularly beneficial for logic cell track height scaling. In this paper, we evaluate the reliability concerns of FSH FETs by experimental comparison with nanosheets (NSH) FETs co-integrated on a single wafer. We report no supplementary charge trapping phenomena being observed notwithstanding the presence of a SiN wall in the FSH architecture. After accounting for processing imperfections (a high-resistive contact to one of both channels) in the FSH device, we conclude that both bias temperature instabilities (BTI) and hot carrier degradation (HCD) reliability are comparable in FSH and NSH. Joint with theoretical calculations of expected horizontal electric fields and worst-case charge trap densities in the SiN dielectric wall in CMOS implementation, we conclude that introducing the FSH architecture does not constitute additional reliability concerns.