Gate Reliability of p-GaN Power HEMTs Under Pulsed Stress Condition

Abstract

A combined experimental/simulation analysis has been performed to study the gate reliability of GaN-HEMTs with p-type gate under pulse stress conditions. Results show that the time-dependent gate breakdown (TDGB) can be determined by two factors: i) the total ON-time during which the device is subjected to a positive gate bias before the failure; ii) the number of pulses, hence the number of switching phases from OFF- to ON-State and vice versa. The severity of the degradation ascribed to transition phases depends on the OFF-time (t(OF)F) and transition time (t(TR) = t(RISE) = t(FALL)). In particular, the shorter tOFF and tTR, the higher the Schottky junction voltage drop and the current peak during the switching phase, respectively. The higher voltage drop is ascribed to the semi-floating potential of the p-GaN layer.