Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling

Abstract

We report on vertically stacked nanosheet (NS) FETs, focusing on the combined inner spacers and source/drain (S/D) epitaxial growth modules sequence, a key integration flow differentiator as compared to finFETs, addressing the impact and control of parasitics and channel strain engineering. The use of both wafer sides for device connection, via nTSVs landing on buried power rails (BPR) after extreme wafer thinning, is also discussed. This configuration is shown to be advantageous for obtaining reduced IR drop values and for, overall, enabling enhanced performance and additional area scaling. It also has the potential to further expand such as to include extra options, together with novel devices/circuits and for various applications.