Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network

Abstract

In this work, we comprehensively evaluate the impact of using backside power delivery network (BSPDN) for CPU of 2D and 3D designs at A14 node from the aspects of power, performance, area and thermal (PPAT) compared to identical designs of conventional front-side (FS) PDN. 2D BSPDN power consumption is 57% smaller than that of 2D FSPDN at iso-CPU frequency. 3D CPU-on-CPU PDN power consumption shows similar to 3.8 totally (or similar to 1.9/CPU) times the 2D FSPDN counterpart. Ring oscillator evaluation shows that logic gates in the IR-drop hotspot region of CPU has worst performance loss <9% and >16% for BSPDN and FSPDN based CPUs respectively while the 3D top CPU can suffer from 25% performance loss. BSPDN based CPU area can be scaled down by 8% compared with the FSPDN counterpart with similar power and performance after physical design and PPA evaluation. Due to the thinning of substrate thickness and the BSPDN process, BSPDN based CPU local temperature can be similar to 40% more than the FSPDN counterpart, illustrating the importance of considering the heat dissipation for the chips with BSPDN. For the CPU-on-CPU 3D IC with power source/package on the bottom and cooler on the top, the top CPU die has 39% more IR drop than the bottom one while the later has 17% more temperature than the former. This opposite trend may induce additional challenge of power integrity and thermal reliability co-design and optimization for 3D ICs with BSPDN.