Time Evolution of DIBL in Gate-All-Around Nanowire MOSFETs During Hot-Carrier Stress

Abstract

The influence of hot-carrier degradation (HCD) on lateral trap distribution within the device channel is experimentally investigated for gate-all-around nanowire (NW) nFETs. In particular, using drain-induced barrier lowering (DIBL) as the parameter, the damage caused by hot-carriers (HCs) is monitored for devices with different geometries, including fin width and gate length. It is observed that with the change in NW width, different degrading mechanisms alter the trap distribution during the application of hot-carrier stress. The trap distribution profile which is found to peak at the drain for very narrow NWs gradually turns uniform as width increases. Interestingly, the carrier location and localization remain the same irrespective of the gate lengths of the NWs. In order to understand the implications of device scaling on HC reliability of advanced CMOS devices, the relative contribution of degradation caused by single and multi carriers degradation process is studied. Both the mechanisms are shown to significantly affect the HC damage profile by causing either highly localized or uniform damage along the device channel.