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CMOS Device Scaling by Nanosheet Channel Architectures and New Channel Materials

dc.contributor.authorHoriguchi, Naoto
dc.date.accessioned2023-12-12T10:48:00Z
dc.date.available2023-08-24T17:41:48Z
dc.date.available2023-08-26T20:00:42Z
dc.date.available2023-12-12T10:48:00Z
dc.date.issued2023-06-11
dc.identifier.issn2161-4636
dc.identifier.otherWOS:001035434300001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/42389.3
dc.sourceWOS
dc.titleCMOS Device Scaling by Nanosheet Channel Architectures and New Channel Materials
dc.typeProceedings paper
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.date.embargo2023-06-12
dc.identifier.eisbn978-4-86348-808-3
dc.source.numberofpages2
dc.source.peerreviewyes
dc.subject.disciplineElectrical & electronic engineering
dc.source.beginpage1
dc.source.endpage2
dc.source.conference26th Silicon Nanoelectronics Workshop (SNW)
dc.source.conferencedateJUN 11-12, 2023
dc.source.conferencelocationKyoto
dc.source.journalna
imec.availabilityPublished - open access


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320.500.12860/42389.3*2023-12-12T10:46:21Zvalidation by library/open access desk
220.500.12860/42389.22023-08-26T19:45:14Zvalidation by imec author
120.500.12860/423892023-08-24T17:41:48Z

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