3D interconnects for quantum computing

Abstract

In this paper, the development of 3D superconducting (SC) interconnects including SC microbumps, through silicon vias (TSVs) and pads on 300mm Si wafers for quantum computing application is reported. In particular, indium plating on different SC layers, D2W TCB stacking of indium based microbumps, room temperature (RT) electrical test and failure analysis of stacked samples, critical temperature (Tc) tests of different SC layers, conformality of SC layers depositions inside high aspect ratio TSVs, hollow TSV and Cu filled TSV process flows, the development of RT PVD alpha-Ta layer and CMP of SC layers on full thickness and thinned 50 mu m thick Si wafers together with electrical measurement of TSV chains, are reported. The development of these 3D building blocks on 300mm silicon wafers using advanced foundry tools is essential for up-scaling qubits to enable the path towards large-scale, error-corrected quantum processors.