Impact of Pitch Scaling on 3D Die-to-Die Interconnects

Abstract

This work explores the advancements and challenges in 3D IC stacking. Unlike traditional 2D planar ICs, 3D stacking vertically integrates multiple layers of circuits, offering improved performance, efficiency, and miniaturization. While this technology has been widely adopted for memory devices, it is less widely used for logic applications because of the challenges of stacking more than two dies. This study investigates the technological challenges and the impact of microbumps, hybrid bonding pads, and TSV pitch scaling on die-to-die interconnect performance. Results indicate that reducing interconnection pitch enhances data rate, bandwidth density, delay, and energy efficiency. Various stacking configurations and interconnection pitches are examined, showing promising results. Advanced stacking technologies like hybrid bonding mitigate performance gaps between 2 and 16 die stacks. Additionally, the study evaluates one-to-one and one-to-many interconnect links, revealing negligible differences in performance. Overall, this research provides insights into optimizing 3D IC stacking for enhanced circuit performance and capacity.