A Scalable Dynamic Segmented Bus Interconnect for Neuromorphic Architectures

Abstract

Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. We propose ADIONA, a dynamic segmented bus interconnect to address design scalability while reducing energy and latency of spike traffic. ADIONA consists of parallel bus lanes arranged in a ladder-shaped structure that allows any tile to connect to another, offers multiple routing options for communication links, and provides a high level of customization for different mapping scenarios and use cases. Each lane in the ladder bus is partitioned into segments using lightweight bufferless switches. Based on compile-time communication information, these switches can be dynamically reconfigured at runtime to execute the target application. Our dynamic segmented bus interconnect substantially enhances hardware utilization, improves fault tolerance, and offers adaptability to execute different applications on a single hardware platform. We evaluate ADIONA using three synthetic and three realistic machine learning workloads on a cycle-accurate neuromorphic simulator. Our results show that ADIONA reduces energy consumption by 2.1 x, latency by 40 x , and interconnect area by 2x , compared to a state-of-the-art interconnect for neuromorphic systems.