Thermal Insights into 3D Packaging of a HighPerformance Server SoC in Advanced Nanosheet Technology

Abstract

This paper evaluates the thermal reliability of 3D packaging for high-performance server system-on-chip (SoC) considering wafer-to-wafer hybrid bonding and backside power delivery network (BS-PDN) in an advanced nanosheet A10 technology node. The hotspot location is observed in the logic die in case of memory-on-logic (MoL) partitioning, which shifts to the memory die for logic-on-memory (LoM) partitioning, due to the higher thermal resistance of the secondary heat dissipation path towards printed-circuit-board (PCB). A holistic co-optimization considering the convective heat transfer coefficient and thermal interface material (TIM) thermal conductivity with respect to the cooling solution is performed. In addition, we observe the impact of non-uniform power distribution in the logic die on thermal reliability similar to +/- 15% over uniform conditions. Lastly, we explore the influence of time-dependent power dissipation on thermal variation, reporting Delta T-Max similar to 18.3 K to 65.6K for the SoC area of 786 mm(2) in A10 node.