Design Space Exploration of FeRAM Bit Cell for DRAM Application

Abstract

HfOx-based ferroelectric random access memories (FeRAMs) have been proposed as a promising candidate to further dynamic random access memory (DRAM) scaling. This article presents a bitcell design space exploration of HfZrOx -based FeRAM based on a 2T1C testbench representative of a 64-kb 1T1C subarray at 40-nm CMOS technology. We first explore the impact of ferroelectric capacitor (FeCAP) sizing on the read sensing margin (SM) and speed with eight different blocks in the subarray, supported by a hardware-calibrated FeCAP compact model. We identify the capacitance ratio (C-R) between the bitline parasitic capacitance (C-BL) and the FeCAP capacitance (C-FE) as the critical design parameter for bitcell SM optimization, with a maximum C-R of 41 permitted for the given FeCAP technology. Furthermore, we investigate the impact of FeCAP sizing on ferro-grain granularity (FGG)-induced variability. Our findings clarify that SM variability worsens with increasing FeCAP size but does not significantly affect the readability overall. Additionally, we examine the consequences of FeCAP sizing on disturbance effects during write operations, concluding that larger FeCAPs help mitigate write disturbances by reducing voltage transfer to half-selected (HS) cells.